C8051F91X-C8051F90X 查看數據表（PDF） - Silicon Laboratories

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C8051F91X-C8051F90X

Single/Dual Battery, 0.9–3.6 V, 16–8 kB, SmaRTClock, 12/10-Bit ADC MCU

Silicon Laboratories 

C8051F91x-C8051F90x

26.3.4. Frequency Output Mode

Frequency Output Mode produces a programmable-frequency square wave on the module’s associated

CEXn pin. The capture/compare module high byte holds the number of PCA clocks to count before the

output is toggled. The frequency of the square wave is then defined by Equation 26.1.

FCEXn

=

---------------F----P---C---A---------------

2  PCA0CPHn

Note: A value of 0x00 in the PCA0CPHn register is equal to 256 for this equation.

Equation 26.1. Square Wave Frequency Output

Where FPCA is the frequency of the clock selected by the CPS2–0 bits in the PCA mode register,

PCA0MD. The lower byte of the capture/compare module is compared to the PCA counter low byte; on a

match, CEXn is toggled and the offset held in the high byte is added to the matched value in PCA0CPLn.

Frequency Output Mode is enabled by setting the ECOMn, TOGn, and PWMn bits in the PCA0CPMn

register. Note that the MATn bit should normally be set to 0 in this mode. If the MATn bit is set to 1, the

CCFn flag for the channel will be set when the 16-bit PCA0 counter and the 16-bit capture/compare

register for the channel are equal.

Write to

PCA0CPLn

0

ENB

Reset

Write to

PCA0CPHn ENB

1

PCA0CPMn

P ECCMT P E

WCA A AOWC

MOP P TGMC

1 MPN n n n F

6nnn

n

n

x 000

x

PCA0CPLn

Enable

8-bit

Comparator

8-bit Adder

PCA0CPHn

Adder

Enable

Toggle

match

TOGn

0 CEXn Crossbar

1

Port I/O

PCA Timebase

PCA0L

Figure 26.7. PCA Frequency Output Mode

300

Rev. 1.0

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