C8051F91X-C8051F90X 查看數據表（PDF） - Silicon Laboratories

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C8051F91X-C8051F90X

Single/Dual Battery, 0.9–3.6 V, 16–8 kB, SmaRTClock, 12/10-Bit ADC MCU

Silicon Laboratories 

C8051F91x-C8051F90x

26.3.1. Edge-triggered Capture Mode

In this mode, a valid transition on the CEXn pin causes the PCA to capture the value of the PCA

counter/timer and load it into the corresponding module's 16-bit capture/compare register (PCA0CPLn and

PCA0CPHn). The CAPPn and CAPNn bits in the PCA0CPMn register are used to select the type of

transition that triggers the capture: low-to-high transition (positive edge), high-to-low transition (negative

edge), or either transition (positive or negative edge). When a capture occurs, the Capture/Compare Flag

(CCFn) in PCA0CN is set to logic 1. An interrupt request is generated if the CCFn interrupt for that module

is enabled. The CCFn bit is not automatically cleared by hardware when the CPU vectors to the interrupt

service routine, and must be cleared by software. If both CAPPn and CAPNn bits are set to logic 1, then

the state of the Port pin associated with CEXn can be read directly to determine whether a rising-edge or

falling-edge caused the capture.

PCA0CPMn

P ECCMT P E

WCA A AOWC

MOP P TGMC

1 MPN n n n F

6nnn

n

n

xx

000x

PCA Interrupt

PCA0CN

CC

CCC

FR

CCC

FFF

210

Port I/O

Crossbar CEXn

0

1

0

1

PCA0CPLn PCA0CPHn

Capture

PCA

Timebase

PCA0L

PCA0H

Figure 26.4. PCA Capture Mode Diagram

Note: The CEXn input signal must remain high or low for at least 2 system clock cycles to be recognized by the

hardware.

Rev. 1.0

297

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