C8051T603-GS(2007) 查看數據表（PDF） - Silicon Laboratories

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C8051T603-GS
(Rev.:2007)

Mixed Signal OTP EPROM MCU Family

Silicon Laboratories 

C8051T600/1/2/3/4/5

Table 5.1. ADC0 Electrical Characteristics

VDD = 3.0 V, VREF = 2.50 V (REFSL = 0), PGA Gain = 1, –40 to +85 °C unless otherwise specified.

Parameter

Conditions

Min

Typ

Max Units

DC Accuracy

Resolution

10

bits

Integral Nonlinearity

—

±0.5

±1

LSB

Differential Nonlinearity

Guaranteed Monotonic

—

±0.5

±1

LSB

Offset Error1

—

TBD

TBD

LSB

Full Scale Error1

—

TBD

TBD

LSB

Dynamic Performance (10 kHz sine-wave input, 1 dB below Full Scale, 500 ksps)

Signal-to-Noise Plus Distortion

TBD

TBD

—

dB

Total Harmonic Distortion

Up to the 5th harmonic

—

TBD

—

dB

Spurious-Free Dynamic Range

—

TBD

—

dB

Conversion Rate

SAR Conversion Clock2,3

Conversion Time in SAR Clocks

10-bit Mode

8-bit Mode

Track/Hold Acquisition Time

VDD > 2.0 V

VDD < 2.0 V

Throughput Rate3

—

—

8.33

MHz

13

11

—

—

clocks

clocks

300

—

—

ns

2.0

0.3

—

µs

—

—

500

ksps

Analog Inputs

Absolute Voltage on External

ADC Input

Input Voltage Range (Gain = 1x) AIN – GND

SAR Sampling Capacitor

1x Gain

0.5x Gain

Temperature Sensor

Linearity1,4

Slope4

Slope Error1,4

Offset4

Temp = 0 °C

Offset Error1,4

Temp = 0 °C

GND – 0.3

0

—

—

—

—

—

—

—

—

—

—

5

3

TBD

3.2

±80

903

±10

VDD + 0.3 V

VREF

V

—

pF

—

pF

—

—

°C

— mV / °C

—

µV/C

—

mV

—

mV

Power Specifications

Power Supply Current

(VDD supplied to ADC0)

Power Supply Rejection

Operating Mode, 500 ksps

—

400

900

µA

—

TBD

—

mV/V

Notes:

1. Represents mean ± one standard deviation.

2. When using the C8051F300 for code development, SAR clock should be limited to 6 MHz.

3. See Section “18. Revision Specific Behavior” on page 159.

4. Includes ADC offset, gain, and linearity variations.

44

Rev. 0.5

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