C8051F38C-GMR 查看數據表（PDF） - Silicon Laboratories
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C8051F38C-GMR Datasheet PDF : 321 Pages
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C8051F380/1/2/3/4/5/6/7/C
Table 22.6. SMBus Status Decoding: Hardware ACK Enabled (EHACK = 1) (Continued)
Values Read
Values to
Write
Current SMbus State
Typical Response Options
Set ACK for next data byte;
Read SMB0DAT.
0 0 1 1000
0
0
1
A master data byte was
received; ACK sent.
Set NACK to indicate next data
byte as the last data byte;
Read SMB0DAT.
Initiate repeated START.
0 0 0 1000
1 0 0 1110
1000
Switch to Master Transmitter
0 0 X 1100
Mode (write to SMB0DAT before
clearing SI).
Read SMB0DAT; send STOP. 0 1 0 —
A master data byte was
0 0 0 received; NACK sent (last
byte).
Read SMB0DAT; Send STOP
followed by START.
1 1 0 1110
Initiate repeated START.
1 0 0 1110
Switch to Master Transmitter
0 0 X 1100
Mode (write to SMB0DAT before
clearing SI).
0
0
0
A slave byte was transmitted;
NACK received.
No action required (expecting
STOP condition).
0 0 X 0001
0100
0
0
1
A slave byte was transmitted;
ACK received.
Load SMB0DAT with next data
byte to transmit.
0 0 X 0100
0
1
X
A Slave byte was transmitted;
error detected.
No action required (expecting
Master to end transfer).
0 0 X 0001
An illegal STOP or bus error
0101 0 X X was detected while a Slave Clear STO.
Transmission was in progress.
00X —
230
Rev. 1.4
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