C8051F38C-GMR 查看數據表（PDF） - Silicon Laboratories

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C8051F38C-GMR

Full Speed USB Flash MCU Family

Silicon Laboratories 

C8051F380/1/2/3/4/5/6/7/C

SFR Definition 22.11. SMB1DAT: SMBus Data

Bit

7

6

5

4

3

2

1

0

Name

SMB1DAT[7:0]

Type

R/W

Reset

0

0

0

0

0

0

0

0

SFR Address = 0xC2; SFR Page = F

Bit

Name

Function

7:0 SMB1DAT[7:0] SMBus1 Data.

The SMB1DAT register contains a byte of data to be transmitted on the SMBus1

serial interface or a byte that has just been received on the SMBus1 serial inter-

face. The CPU can read from or write to this register whenever the SI1 serial inter-

rupt flag (SMB1CN.0) is set to logic 1. The serial data in the register remains stable

as long as the SI1 flag is set. When the SI1 flag is not set, the system may be in the

process of shifting data in/out and the CPU should not attempt to access this regis-

ter.

222

Rev. 1.4

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