C8051F38C-GMR 查看數據表（PDF） - Silicon Laboratories

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C8051F38C-GMR

Full Speed USB Flash MCU Family

Silicon Laboratories 

C8051F380/1/2/3/4/5/6/7/C

SFR Definition 22.2. SMB1CF: SMBus Clock/Configuration

Bit

7

6

5

4

3

2

1

0

Name ENSMB1 INH1

BUSY1 EXTHOLD1 SMB1TOE SMB1FTE

SMB1CS[1:0]

Type R/W

R/W

R

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

SFR Address = 0xC1; SFR Page = F

Bit

Name

Function

7 ENSMB1 SMBus1 Enable.

This bit enables the SMBus1 interface when set to 1. When enabled, the interface

constantly monitors the SDA1 and SCL1 pins.

6

INH1

SMBus1 Slave Inhibit.

When this bit is set to logic 1, the SMBus1 does not generate an interrupt when

slave events occur. This effectively removes the SMBus1 slave from the bus. Mas-

ter Mode interrupts are not affected.

5

BUSY1 SMBus1 Busy Indicator.

This bit is set to logic 1 by hardware when a transfer is in progress. It is cleared to

logic 0 when a STOP or free-timeout is sensed.

4 EXTHOLD1 SMBus1 Setup and Hold Time Extension Enable.

This bit controls the SDA1 setup and hold times according to Table 22.2.

0: SDA1 Extended Setup and Hold Times disabled.

1: SDA1 Extended Setup and Hold Times enabled.

3 SMB1TOE SMBus1 SCL Timeout Detection Enable.

This bit enables SCL low timeout detection. If set to logic 1, the SMBus1 forces

Timer 4 to reload while SCL1 is high and allows Timer 4 to count when SCL1 goes

low. If Timer 4 is configured to Split Mode, only the High Byte of the timer is held in

reload while SCL1 is high. Timer 4 should be programmed to generate interrupts at

25 ms, and the Timer 4 interrupt service routine should reset SMBus1 communica-

tion.

2 SMB1FTE SMBus1 Free Timeout Detection Enable.

When this bit is set to logic 1, the bus will be considered free if SCL1 and SDA1

remain high for more than 10 SMBus clock source periods.

1:0 SMB1CS[1:0] SMBus1 Clock Source Selection.

These two bits select the SMBus1 clock source, which is used to generate the

SMBus1 bit rate. The selected device should be configured according to

Equation 22.1.

00: Timer 0 Overflow

01: Timer 5 Overflow

10: Timer 2 High Byte Overflow

11: Timer 2 Low Byte Overflow

212

Rev. 1.4

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