C8051F362-GM2 查看數據表（PDF） - Silicon Laboratories

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C8051F362-GM2

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F360/1/2/3/4/5/6/7/8/9

SFR Definition 17.23. P3MDOUT: Port3 Output Mode

SFR Page: F

SFR Address: 0xAF

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Bits 7–0: Output Configuration Bits for P3.7-P3.0 (respectively): ignored if corresponding bit in regis-

ter P3MDIN is logic ‘0’.

0: Corresponding P3.n Output is open-drain.

1: Corresponding P3.n Output is push-pull.

SFR Definition 17.24. P3SKIP: Port3 Skip

SFR Page: F

SFR Address: 0xD7

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Bits 7–0: P3SKIP[7:0]: Port3 Crossbar Skip Enable Bits.

These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as ana-

log inputs (for ADC or Comparator) or used as special functions (VREF input, external oscil-

lator circuit, CNVSTR input) should be skipped by the Crossbar.

0: Corresponding P3.n pin is not skipped by the Crossbar.

1: Corresponding P3.n pin is skipped by the Crossbar.

Rev. 1.0

199

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