C8051F362-GM2 查看數據表（PDF） - Silicon Laboratories

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C8051F362-GM2

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F360/1/2/3/4/5/6/7/8/9

SFR Definition 17.6. P0SKIP: Port0 Skip

SFR Page: F

SFR Address: 0xD4

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset Value

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Bits 7–0: P0SKIP[7:0]: Port0 Crossbar Skip Enable Bits.

These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as ana-

log inputs (for ADC or Comparator) or used as special functions (VREF input, external oscil-

lator circuit, CNVSTR input) should be skipped by the Crossbar.

0: Corresponding P0.n pin is not skipped by the Crossbar.

1: Corresponding P0.n pin is skipped by the Crossbar.

SFR Definition 17.7. P0MAT: Port0 Match

SFR Page: 0

SFR Address: 0xF3

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset Value

11111111

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Bits 7–0: P0MAT[7:0]: Port0 Match Value.

These bits control the value that unmasked P0 Port pins are compared against. A Port

Match event is generated if (P0 & P0MASK) does not equal (P0MAT & P0MASK).

SFR Definition 17.8. P0MASK: Port0 Mask

SFR Page: 0

SFR Address: 0xF4

R/W

R/W

Bit7

Bit6

R/W

Bit5

R/W

Bit4

R/W

Bit3

R/W

Bit2

R/W

Bit1

R/W

Reset Value

00000000

Bit0

Bits 7–0: P0MASK[7:0]: Port0 Mask Value.

These bits select which Port pins will be compared to the value stored in P0MAT.

0: Corresponding P0.n pin is ignored and cannot cause a Port Match event.

1: Corresponding P0.n pin is compared to the corresponding bit in P0MAT.

192

Rev. 1.0

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