C8051F362-GM2 查看數據表（PDF） - Silicon Laboratories
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C8051F362-GM2 Datasheet PDF : 288 Pages
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C8051F360/1/2/3/4/5/6/7/8/9
Table 16.3. PLL Frequency Characteristics
–40 to +85 °C unless otherwise specified.
Parameter
Conditions
Min Typ Max
Input Frequency
(Divided Reference Frequency)
5
30
PLL Output Frequency
25
100*
*Note: The maximum operating frequency of the C8051F366/7/8/9 is 50 MHz.
Units
MHz
MHz
Input
Frequency
5 MHz
25 MHz
Table 16.4. PLL Lock Timing Characteristics
–40 to +85 °C unless otherwise specified
Multiplier
Pll0flt
Output
Min Typ Max
(Pll0mul)
Setting
Frequency
20
0x0F
100 MHz
202
13
0x0F
65 MHz
115
16
0x1F
80 MHz
241
9
0x1F
45 MHz
116
12
0x2F
60 MHz
258
6
0x2F
30 MHz
112
10
0x3F
50 MHz
263
5
0x3F
25 MHz
113
4
0x01
100 MHz
42
2
0x01
50 MHz
33
3
0x11
75 MHz
48
2
0x11
50 MHz
17
2
0x21
50 MHz
42
1
0x21
25 MHz
33
2
0x31
50 MHz
60
1
0x31
25 MHz
25
Units
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
182
Rev. 1.0
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