C8051F362-GM2 查看數據表（PDF） - Silicon Laboratories

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C8051F362-GM2

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F360/1/2/3/4/5/6/7/8/9

SFR Definition 17.2. XBR1: Port I/O Crossbar Register 1

SFR Page:

F

SFR Address: 0xE2

R/W

R/W

WEAKPUD XBARE

Bit7

Bit6

R/W

T1E

Bit5

R/W

T0E

Bit4

R/W

ECIE

Bit3

R/W

R/W

R/W

Reset Value

PCA0ME

00000000

Bit2

Bit1

Bit0

Bit 7: WEAKPUD: Port I/O Weak Pullup Disable.

0: Weak Pullups enabled (except for Ports whose I/O are configured as analog input).

1: Weak Pullups disabled.

Bit 6: XBARE: Crossbar Enable.

0: Crossbar disabled.

1: Crossbar enabled.

Bit 5: T1E: T1 Enable

0: T1 unavailable at Port pin.

1: T1 routed to Port pin.

Bit 4: T0E: T0 Enable

0: T0 unavailable at Port pin.

1: T0 routed to Port pin.

Bit 3: ECIE: PCA0 External Counter Input Enable

0: ECI unavailable at Port pin.

1: ECI routed to Port pin.

Bits 2–0: PCA0ME: PCA Module I/O Enable Bits.

000: All PCA I/O unavailable at Port pins.

001: CEX0 routed to Port pin.

010: CEX0, CEX1 routed to Port pins.

011: CEX0, CEX1, CEX2 routed to Port pins.

100: CEX0, CEX1, CEX2, CEX3 routed to Port pins.

101: CEX0, CEX1, CEX2, CEX3, CEX4 routed to Port pins.

110: CEX0, CEX1, CEX2, CEX3, CEX4, CEX5 routed to Port pins.

111: Reserved.

Rev. 1.0

189

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