C8051F007 查看數據表（PDF） - Silicon Laboratories
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C8051F007 Datasheet PDF : 171 Pages
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C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
Table 13.1. Reset Electrical Characteristics
-40°C to +85°C unless otherwise specified.
PARAMETER
CONDITIONS
/RST Output Low Voltage IOL = 8.5mA, VDD = 2.7 to 3.6V
/RST Input High Voltage
/RST Input Low Voltage
MIN
0.7 x
VDD
TYP
/RST Input Leakage Current
VDD for /RST Output Valid
AV+ for /RST Output Valid
VDD POR Threshold (VRST)
Reset Time Delay
Missing Clock Detector
Timeout
/RST = 0.0V
/RST rising edge after crossing reset
threshold
Time from last system clock to reset
generation
20
1.0
1.0
2.40 2.55
80
100
100 220
MAX
0.6
0.3 x
VDD
2.70
120
500
UNITS
V
V
V
µA
V
V
V
ms
µs
Rev. 1.7
98
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