C8051F007 查看數據表（PDF） - Silicon Laboratories

零件编号

产品描述 (功能)

生产厂家

C8051F007

Mixed-Signal 32KB ISP FLASH MCU Family

Silicon Laboratories 

C8051F000/1/2/5/6/7

C8051F010/1/2/5/6/7

13.1. Power-on Reset

The C8051F000 family incorporates a power supply monitor that holds the MCU in the reset state until VDD rises

above the VRST level during power-up. (See Figure 13.2 for timing diagram, and refer to Table 13.1 for the

Electrical Characteristics of the power supply monitor circuit.) The /RST pin is asserted (low) until the end of the

100ms VDD Monitor timeout in order to allow the VDD supply to become stable.

On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. All of the other reset

flags in the RSTSRC Register are indeterminate. PORSF is cleared by a reset from any other source. Since all

resets cause program execution to begin at the same location (0x0000), software can read the PORSF flag to

determine if a power-up was the cause of reset. The content of internal data memory should be assumed to be

undefined after a power-on reset.

13.2. Software Forced Reset

Writing a 1 to the PORSF bit forces a Power-On Reset as described in Section 13.1.

Figure 13.2. VDD Monitor Timing Diagram

2.70

2.40

2.0

1.0

VRST

Logic HIGH

/RST

Logic LOW

100ms

t

100ms

13.3. Power-fail Reset

When a power-down transition or power irregularity causes VDD to drop below VRST, the power supply monitor

will drive the /RST pin low and return the CIP-51 to the reset state (see Figure 13.2). When VDD returns to a level

above VRST, the CIP-51 will leave the reset state in the same manner as that for the power-on reset. Note that even

though internal data memory contents are not altered by the power-fail reset, it is impossible to determine if VDD

dropped below the level required for data retention. If the PORSF flag is set, the data may no longer be valid.

Rev. 1.7

94

Share Link: