CS4360(2004) 查看數據表（PDF） - Cirrus Logic

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CS4360
(Rev.:2004)

24-Bit, 192 kHz 6-channel D/A Converter

Cirrus Logic 

CS4360

SDA

001000 AD0 W

ACK

MAP

1-8

ACK

DATA

1-8

ACK

SCL

S ta rt

Figure 19. I²C Write

S top

4.9.2b I²C Read

To read from the device, follow the procedure below while adhering to the control port Switching Specifi-

cations. During this operation it is first necessary to write to the device, specifying the appropriate register

through the MAP.

1) After writing to the MAP (see section 4.9.1), initiate a repeated START condition to the I²C bus fol-

lowed by the address byte. The upper 6 bits must be 001000. The seventh bit must match the setting

of the AD0 pin, and the eighth must be 1. The eighth bit of the address byte is the R/W bit.

2) Signal the end of the address byte by not issuing an acknowledge. The device will then transmit the

contents of the register pointed to by the MAP. The MAP will contain the address of the last register

written to the MAP.

3) If the INCR bit is set to 1, the device will continue to transmit the contents of successive registers. Con-

tinue providing a clock but do not issue an ACK on the bytes clocked out of the device. After all the

desired registers are read, initiate a STOP condition to the bus.

4) If the INCR bit is set to 0 and further I²C reads from other registers are desired, it is necessary to repeat

the procedure detailed from step 1. If no further reads from other registers are desired, initiate a STOP

condition to the bus.

SDA

001000 AD0 W

ACK

M AP

1-8

ACK

001000 AD0 R

ACK

Data 1-8

(po in te d to b y MA P)

ACK

Data 1-8

(p oin te d to b y MA P)

SCL

S ta rt

R epeated STAR T

or

Aborted W R ITE

S to p

Figure 20. I²C Read

4.9.3 SPI Mode

In SPI mode, data is clocked into the serial control data line, CDIN, by the serial control port clock, CCLK

(see Figure 21 for the clock to data relationship). There is no AD0 pin. Pin CS is the chip select signal and

is used to control SPI writes to the control port. When the device detects a high-to-low transition on the

AD0/CS pin after power-up, SPI mode will be selected. All signals are inputs and data is clocked in on the

rising edge of CCLK.

DS517F2

27

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