CS4360(2004) 查看數據表（PDF） - Cirrus Logic

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CS4360
(Rev.:2004)

24-Bit, 192 kHz 6-channel D/A Converter

Cirrus Logic 

CS4360

4.3.2 Control Port Mode

The desired format is selected via the DIF2, DIF1 and DIF0 bits in the Mode Control 2 register (see section

6.1.2). For an illustration of the required relationship between LRCK, SCLK and SDIN, see Figures 15-17.

LRCK

SCLK

SD IN

Left C hannel

R ig ht C hannel

MSB -1 -2 -3 -4 -5

+5 +4 +3 +2 +1 LSB

MSB -1 -2 -3 -4

+5 +4 +3 +2 +1 LSB

Figure 15. Left Justified up to 24-Bit Data

LRCK

SCLK

S D IN

Left C hannel

R ig ht C hannel

MSB -1 -2 -3 -4 -5

+5 +4 +3 +2 +1 LSB

MSB -1 -2 -3 -4

Figure 16. I2S, up to 24-Bit Data

+5 +4 +3 +2 +1 LSB

LRCK

SCLK

Left Channel

Right Cha nnel

SDIN

LSB

MSB -1 -2 -3 -4 -5

+7 +6 +5 +4 +3 +2 +1 LSB

MSB -1 -2 -3 -4 -5

+7 +6 +5 +4 +3 +2+1 LSB

Figure 17. Right Justified Data

4.4 De-Emphasis Control

The device includes on-chip digital de-emphasis. Figure 18 shows the de-emphasis curve for Fs equal to

44.1 kHz. The frequency response of the de-emphasis curve will scale proportionally with changes in

sample rate, Fs.

Gain

dB

T1=50 µs

0dB

-10dB

T2 = 15 µs

F1

3.183 kHz

F2 Frequency

10.61 kHz

Figure 18. De-emphasis Curve

Notes: De-emphasis is only available in Single-speed Mode.

DS517F2

23

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