CS61880-IB 查看數據表（PDF） - Cirrus Logic

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CS61880-IB

Octal E1 Line Interface Unit

Cirrus Logic 

CS61880

19.5 Receiver Analog Characteristics

(TA = -40° C to 85° C; TV+, RV+ = 3.3 V ±5%; GND = 0 V))

Parameter

Min.

Typ

Max

Units

Allowable Cable Attenuation @ 1024kHz and 772kHz

-

-

- 12

dB

RTIP/RRING Input Impedance

(Internal Line matching mode)

Note 10

RTIP/RRING Input Impedance

(External Line matching mode)

Note 10

Receiver Dynamic Range

E1 120 Ω Load -

13k

-

Ω

E1 75Ω Load -

50

-

E1 120 Ω Load -

13k

-

Ω

E1 75Ω Load -

13K

-

0.5

-

-

Vp

Signal to Noise margin (Per G.703, O151 @ 6dB cable Atten).

-

-18

-

dB

Receiver Squelch Level

150

mV

LOS Threshold

-

200

-

mV

LOS Hysteresis

50

mV

Data Decision Threshold

Note 10

Input Jitter Tolerance

Notes 10, 14, 16

42

50

58

% of

peak

1 Hz - 1.8 Hz 18

-

-

UI

20 Hz - 2.4 kHz 1.5

-

-

18 kHz - 100 kHz 0.2

-

-

Input Return Loss

Notes 10, 11, 12

51 kHz - 102 kHz -18

-28

-

dB

102 kHz - 2048 kHz -18

-30

-

2048 kHz - 3072 kHz -18

-27

-

Notes: 10. Parameters guaranteed by design and characterization.

11. Using components on the CDB61880 evaluation board in Internal Match Impedance Mode.

12. Return loss = 20log10 ABS((Z1 + Z0) / (Z1 - Z0)) where Z1 - impedance of the transmitter or receiver,

and Z0 = cable impedance.

13. Assuming that jitter free clock is input to TCLK.

14. Jitter tolerance for 6 dB input signal levels. Jitter tolerance increases at lower frequencies. HDB3 coders

enabled.

15. In Data Recovery Mode.

16. Jitter Attenuator in the receive path.

DS450PP2

55

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