CS1880-IB 查看數據表（PDF） - Cirrus Logic
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CS1880-IB Datasheet PDF : 70 Pages
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CS61880
TPOS
TNEG
TCLK
Transmit
Control &
Pulse Shaper
TTIP
TRING
RPOS
RNEG
RCLK
Clock Recovery &
Data Recovery
RTIP
RRING
MCLK
TAOS
TPOS
TNEG
TCLK
RPOS
RNEG
RCLK
Figure 7. Analog Loopback Block Diagram
Transmit
Control &
Pulse Shaper
Clock Recovery &
Data Recovery
TTIP
TRING
(All One's)
RTIP
RRING
Figure 8. Analog Loopback with TAOS Block Diagram
12.3 Digital Loopback
12.4 Remote Loopback
Digital Loopback causes the TCLK, TPOS, and
TNEG (or TDATA) inputs to be looped back
through the jitter attenuator (if enabled) to the
RCLK, RPOS, and RNEG (or RDATA) outputs.
The receive line interface is ignored, but data at
TPOS and TNEG (or TDATA) continues to be
transmitted to the line interface at TTIP and
TRING (Refer to Figure 9 on page 31).
Digital Loopback is only available during host
mode. It is selected using the appropriate bit in the
Digital Loopback Reset Register (0Ch) (See Sec-
tion 14.13 on page 36).
NOTE: TAOS can also be used during the Digital Loop-
back operation for the selected channel (Refer
to Figure 10 on page 31).
In remote loopback, the RPOS/RNEG and RCLK
outputs are internally input to the transmit circuits
for output on TTIP/TRING. In this mode the
TCLK, TPOS and TNEG inputs are ignored. (Refer
to Figure 11 on page 31). In hardware mode, Re-
mote Loopback is selected by driving the LOOP
pin for a certain channel low. In host mode, Remote
Loopback is selected for a given channel by writing
a one to the appropriate bit in the Remote Loop-
back Register (02h) (See Section 14.3 on
page 35).
NOTE: In hardware mode, Remote Loopback over-
rides TAOS for the selected channel. In host
mode, TAOS overrides Remote Loopback.
30
DS450PP2
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