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ASM2P5T905A
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ASM2P5T905A 데이터시트 - PulseCore Semiconductor
PulseCore Semiconductor
Functional Description
The ASM2P5T905A 2.5V single data rate (SDR) Clock buffer is a user-selectable single-ended or differential input to five single-ended outputs buffer built on advanced metal CMOS technology. The SDR Clock buffer fanout from a single or differential input to five single-ended outputs reduces the loading on the preceding driver and provides an efficient clock distribution network. The ASM2P5T905A can act as a translator from a differential HSTL, eHSTL, 1.8V/2.5V LVTTL, LVEPECL or single-ended 1.8V/2.5V LVTTL input to HSTL, eHSTL, 1.8V/2.5V LVTTL outputs. Selectable interface is controlled by 3 level input signals that may be hard-wired to appropriate high-mid-low levels. Multiple power and grounds reduce noise.
Features
• Guaranteed Low Skew < 25pS (max)
• Very low duty cycle distortion
• High speed propagation delay < 2.5nS. (max)
• Up to 250MHz operation
• Very low CMOS power levels
• 1.5V VDDQ for HSTL interface
• Hot insertable and Over-voltage tolerant inputs
• 3 level inputs for selectable interface
• Selectable HSTL, eHSTL, 1.8V / 2.5V LVTTL, or
LVEPECL input interface
• Selectable differential or single-ended inputs and
five single ended outputs
• 2.5V Supply Voltage
• Available in TSSOP Package
Applications:
ASM2P5T905A is targeted towards Clock and signal distribution.
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