CS8900 데이터 시트보기 (PDF) - Cirrus Logic
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CS8900 Datasheet PDF : 132 Pages
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CS8900
Register 13: Line Control (LineCTL, Read/Write)
Address: PacketPage base + 0112h
F
E
D
C
B
A
9
8
7
6
5-0
LoRx
Squelch
2-part PolarityDis Mod
DefDis
BackoffE
Auto
AUIonly SerTxON SerRxON 010011
AUI/10BT
LineCTL determines the configuration of the MAC engine and physical interface.
BIT NAME
5-0 010011
6
SerRxON
7
SerTxON
8
AUIonly
DESCRIPTION
These bits provide an internal address used by the CS8900 to identify this as the Line
Control Register. To write to this register, these bits must be 010011, where the LSB
corresponds to Bit 0.
When set, the receiver is enabled. When clear, no incoming packets pass through the
receiver. If SerRxON is cleared while a packet is being received, reception is completed
and no subsequent receive packets are allowed until SerRxON is set again.
When set, the transmitter is enabled. When clear, no transmissions are allowed. If
SerTxON is cleared while a packet is being transmitted, transmission is completed and
no subsequent packets are transmitted until SerTxON is set again.
Bits 8 and 9 are used to select either the AUI or the 10BASE-T interface according to
the following: [Note: 10BASE-T transmitter will be inactive even when selected unless
link pulses are detected or bit DisableLT (register 19) is set.]
AUIonly (Bit 8)
AutoAUI/10BT (Bit 9)
Physical Interface
1
N/A
AUI
0
0
10BASE-T
0
1
Auto-Select
9
AutoAUI/10BT See AUIonly (Bit 8) description above.
B
ModBackoffE When clear, the ISO/IEC standard backoff algorithm is used (see Section 3.9). When
set, the Modified Backoff algorithm is used. (The Modified Backoff algorithm extends the
backoff delay after each of the first three Tx collisions.)
C PolarityDis
The 10BASE-T receiver automatically determines the polarity of the received signal at
the RXD+/RXD- input (see Section 3.11). When this bit is clear, the polarity is corrected,
if necessary. When set, no effort is made to correct the polarity. This bit is independent
of the PolarityOK bit (Register 14, LineST, Bit C), which reports whether the polarity is
normal or reversed.
D 2-partDefDis Before a transmission can begin, the CS8900 follows a deferral procedure. With the
2-partDefDis bit clear, the CS8900 uses the standard two-part deferral as defined in
ISO/IEC 8802-3 paragraph 4.2.3.2.1. With the 2-partDefDis bit set, the two-part deferral
is disabled.
E
LoRxSquelch When clear, the 10BASE-T receiver squelch thresholds are set to levels defined by the
ISO/IEC 8802-3 specification. When set, the thresholds are reduced by approximately
6 dB. This is useful for operating with "quiet" cables that are longer than 100 meters.
After reset, if no EEPROM is found by the CS8900, then the register has the following initial state. If an
EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3.
0000 0000 0001 0011
60
DS150PP2
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