CS8900 데이터 시트보기 (PDF) - Cirrus Logic
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CS8900 Datasheet PDF : 132 Pages
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CS8900
Register B: Buffer Configuration (BufCFG, Read/Write)
Address: PacketPage base + 010Ah
F
E
RxDestiE
D
Miss
OvfloiE
C
TxCol
OvfloiE
B
Rx128iE
A
RxMissiE
9
TxUnder
runiE
8
7
Rdy4TxiE RxDMAiE
6
SWint-X
5-0
001011
Each bit in BufCFG is an interrupt enable. When set, the interrupt described below is enabled. When clear, there
is no interrupt.
BIT NAME
DESCRIPTION
5-0 001011
These bits provide an internal address used by the CS8900 to identify this as the Buffer
Configuration Register. To write to this register, these bits must be 001011, where the
LSB corresponds to Bit 0.
6
SWint-X
When set, there is an interrupt requested by the host software. The CS8900 provides
the interrupt, and sets the SWint (Register C, BufEvent, Bit 6) bit. The CS8900 acts
upon this command at once. SWint-X is an Act-Once bit. To generate another interrupt,
re-write a "1" to this bit.
7
RxDMAiE
When set, there is an interrupt when a frame has been received and DMA is complete.
With this interrupt, the RxDMAFrame bit (Register C, BufEvent, Bit 7) is set.
8
Rdy4TxiE
When set, there is an interrupt when the CS8900 is ready to accept a frame from the
host for transmission. (See Section 5.7 for a description of the transmit bid process.)
9
TxUnderruniE When set, there is an interrupt if the CS8900 runs out of data before it reaches the end
of the frame (called a transmit underrun). When this happens, event bit TXUnderrun
(Register C, BufEvent, Bit 9) is set and the CS8900 makes no further attempts to
transmit that frame. If the host still wants to transmit that particular frame, the host must
go through the transmit request process again.
A
RxMissiE
When set, there is an interrupt if one or more received frames is lost due to slow
movement of receive data out of the receive buffer (called a receive miss). When this
happens, the RxMiss bit (Register C, BufEvent, Bit A) is set.
B
Rx128iE
When set, there is an interrupt after the first 128 bytes of a frame have been received.
This allows a host processor to examine the Destination Address, Source Address,
Length, Sequence Number, and other information before the entire frame is received.
This interrupt should not be used with DMA. Thus, if either AutoRxDMA (Register 3,
RxCFG, Bit A) or RxDMAonly (Register 3, RxCFG, Bit 9) is set, the Rx128iE bit must
be clear.
C TxColOvfiE If set, there is an interrupt when the TxCOL counter increments from 1FFh to 200h.
(The TxCOL counter (Register 18) is incremented whenever the CS8900 sees that the
RXD+/RXD- pins (10BASE-T) or the CI+/CI- pins (AUI) go active while a packet is being
transmitted.)
Continued on the next page.
DS150PP2
55
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