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STM32F103VB 데이터 시트보기 (PDF) - STMicroelectronics

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STM32F103VB Datasheet PDF : 67 Pages
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STM32F103xx
Electrical characteristics
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 25 or Figure 26,
depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be
ceramic (good quality). They should be placed them as close as possible to the chip.
Figure 25. Power supply and reference decoupling (VREF+ not connected to VDDA)
STM32F103xx
VREF+
(see note 1)
1 µF // 10 nF
1 µF // 10 nF
VDDA
VSSA /VREF+
(see note 1)
1. VREF+ and VREF– inputs are available only on 100-pin packages.
ai14388
Figure 26. Power supply and reference decoupling (VREF+ connected to VDDA)
STM32F103xx
VREF+/VDDA
(See note 1)
1 µF // 10 nF
VREF–/VSSA
(See note 1)
1. VREF+ and VREF– inputs are available only on 100-pin packages.
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