CS61884-IB 데이터 시트보기 (PDF) - Cirrus Logic

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CS61884-IB

Octal T1/E1/J1 Line Interface Unit

Cirrus Logic 

CS61884

14.22 AIS Interrupt Status Register (15h)

BIT NAME

Description

Bit n is set to “1” to indicate a change of status of bit n in the AIS Status Register. The bits in

[7:0] AISI 7-0 this register indicate which channel changed in status since the last cleared AIS interrupt.

Register bits default to 00h after power-up or reset.

14.23 AWG Broadcast Register (16h)

BIT NAME

Description

Setting bit n to “1” causes the phase data in the AWG Phase Data Register to be written to

[7:0] AWGB 7-0 the corresponding channel or channels simultaneously. (Refer to Arbitrary Waveform Gen-

erator (See Section 15 on page 43). Register bits default to 00h after power-up or reset.

14.24 AWG Phase Address Register (17h)

BIT NAME

Description

[7:5] AWGA These bits specify the target channel 0-7. (Refer to Arbitrary Waveform Generator (See

Section 15 on page 43). Register bits default to 00h after power-up or reset.

[4:0] PA[4:0] These bits specify 1 of 24 (E1) or 26/28 (T1/J1) phase sample address locations of the AWG,

that the phase data in the AWG Phase Data Register is written to or read from. The other

locations in each channel’s phase sample addresses are not used, and should not be

accessed. Register bits default to 00h after power-up or reset.

14.25 AWG Phase Data Register (18h)

BIT NAME

Description

[7]

RSVD

RESERVED (This bit must be set to 0.)

These bits are used for the pulse shape data that will be written to the AWG phase location

specified by the AWG Phase Address Register. The value written to or read from this register

will be written to or read from the AWG phase sample location specified by the AWG Phase

[6:0] AWGD [6:0] Address register. A software reset through the Software Reset Register does not effect the

contents of this register. The data in each phase is a 7-bit 2’s complement number (the max-

imum positive value is 3Fh and the maximum negative value is 40h). (Refer to Arbitrary

Waveform Generator (See Section 15 on page 43). Register bits default to 00h after

power-up.

14.26 AWG Enable Register (19h)

BIT NAME

Description

The AWG enable register is used for selecting the source of the customized transmission

pulse-shape. Setting bit n to “1” in this register selects the AWG as the source of the output

[7:0] AWGN 7-0 pulse shape for channel n. When bit n is set to “0” the pre-programmed pulse shape in the

ROM is selected for transmission on channel n. (Refer to Arbitrary Waveform Generator

(See Section 15 on page 43). Register bits default to 00h after power-up or reset.

40

DS485F1

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