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CS61884-IB

Octal T1/E1/J1 Line Interface Unit

Cirrus Logic 

CS61884

13. HOST MODE

Host mode allows the CS61884 to be configured

and monitored using an internal register set. (Refer

to Table 1, “Operation Mode Selection,” on

page 10). The term, “Host mode” applies to both

Parallel Host and Serial Host modes.

All of the internal registers are available in both Se-

rial and Parallel Host mode; the only difference is

in the functions of the interface pins, which are de-

scribed in Table 8.

Serial port operation is compatible with the serial

ports of most microcontrollers. Parallel port opera-

tion can be configured to be compatible with 8-bit

microcontrollers from Motorola or Intel, with both

multiplexed or non-multiplexed address/data bus-

ses. (Refer to Table 9 on page 34 for host mode

registers).

13.1 SOFTWARE RESET

A software reset can be forced by writing the Soft-

ware Reset Register (0Ah) (See Section 14.11 on

page 36). A software reset initializes all registers to

their default settings and initializes all internal state

machines.

13.2 Serial Port Operation

Serial port host mode operation is selected when

the MODE pin is left open or set to VCC/2. In this

mode, the CS61884 register set is accessed by set-

ting the chip select (CS) pin low and communicat-

ing over the SDI, SDO, and SCLK pins. Timing

over the serial port is independent of the transmit

and receive system timing. Figure 13 illustrates the

format of serial port data transfers.

A read or write is initiated by writing an ad-

dress/command byte (ACB) to SDI. Only the

ADR0-ADR4 bits are valid; bits ADR5-ADR6 are

do not cares. During a read cycle, the register data

addressed by the ACB is output on SDO on the next

eight SCLK clock cycles. During a write cycle, the

data byte immediately follows the ACB.

Data is written to and read from the serial port in

LSB first format. When writing to the port, SDI

data is sampled by the device on the rising edge of

SCLK. The valid clock edge of the data on SDO is

controlled by the CLKE pin. When CLKE is low,

data on SDO is valid on the falling edge of SCLK.

When CLKE is high, data on SDO is valid on the

raising edge of SCLK. The SDO pin is Hi-Z when

not transmitting. If the host processor has a bidirec-

tional I/O port, SDI and SDO may be tied together.

PIN NAME

MODE

MUX

CODEN/MOT/INTL

ADDR [4]

ADDR[3:0]

LOOP[7:0], DATA[7:0]

INT

SDO/ACK/RDY

LEN0/SDI/DS/WR

LEN1/R/W/RD

LEN2/SCLK/AS/ALE

JASEL/CS

Table 8. Host Control Signal Descriptions

HOST CONTROL SIGNAL DESCRIPTIONS

PIN #

HARDWARE

SERIAL

11

LOW

VDD/2

43

BITSEN0

-

88

CODEN

-

12

GND

-

13-16

ADDR[3:0]

-

28-21

LOOP[7:0]

-

82

Pulled Up

INT

83

NC

SDO

84

LEN0

SDI

85

LEN1

-

86

LEN2

SCLK

87

JASEL

CS

PARALLEL

HIGH

MUX

MOT/INTL

ADDR[4]

ADDR [3:0]

DATA[7:0]

INT

ACK/RDY

DS/WR

R/W/RD

AS/ALE

CS

32

DS485F1

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