CS44L10 데이터 시트보기 (PDF) - Cirrus Logic

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CS44L10

Digital PWM Headphone Monitor

Cirrus Logic 

CS44L10

is decreased until the HP_x outputs reach GND.

The time required to reach GND is determined by

the RMP_SP bits. This allows the DC-blocking ca-

pacitors to slowly discharge. Once this charge is

dissipated, the power to the device may be turned

off, and the system is ready for the next power-on.

To prevent an audio transient at the next power-on,

the DC-blocking capacitors must fully discharge

before turning off the power or exiting the pow-

er-down state. If full discharge does not occur, a

transient will occur when the audio outputs are ini-

tially clamped to GND. The time that the device

must remain in the power-down state is related to

the value of the DC-blocking capacitance and the

output load. For example, with a 220 µF capacitor

and a 16 ohm load on the headphone outputs, the

minimum power-down time will be approximately

0.4 seconds.

Note that ramp up and ramp down period can be set

to zero with the RUPBYP and RDNBYP bits re-

spectively.

6.5 Recommended Power-up Sequence

6.5.1 Stand Alone Mode

1. Hold RST low until the power supply, master,

and left/right clocks are stable. In this state, the

control port is reset to its default settings and the

HP_x lines will remain low.

2. Bring RST high. The device will remain in a low

power state and will initiate the Stand-Alone pow-

er-up sequence. The control port will be accessible

at this time.

6.5.2 Control Port Mode

1. Hold RST low until the power supply, master,

and left/right clocks are stable. In this state, the

control port is reset to its default settings and the

HP_x lines will remain low.

2. Bring RST high. The device will remain in a low

power state and will initiate the Stand-Alone pow-

er-up sequence. The control port will be accessible

at this time.

3. On the CS44L10 the control port pins are shared

with stand-alone configuration pins. To enable the

control port, the user must set the CP_EN bit. This

is done by performing a Two-Wire or SPI write.

Once the control port is enabled, these pins are ded-

icated to control port functionality.

To prevent audible artifacts the CP_EN bit (see

Section 4.10.4) should be set prior to the comple-

tion of the Stand-Alone power-up sequence, ap-

proximately 21mS. Writing this bit will halt the

Stand-Alone power-up sequence and initialize the

control port to its default settings. Note, the CP_EN

bit can be set any time after RST goes high; how-

ever, setting this bit after the Stand-Alone pow-

er-up sequence has completed can cause audible

artifacts.

DS541PP1

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