CS44L10 데이터 시트보기 (PDF) - Cirrus Logic

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CS44L10

Digital PWM Headphone Monitor

Cirrus Logic 

CS44L10

6. APPLICATIONS

6.1 Grounding and Power Supply Decoupling

As with any switching converter, the CS44L10 re-

quires careful attention to power supply and

grounding arrangements to optimize performance.

Figures 3 and 4 show the recommended power ar-

rangement with VD, VA_HPx, and VL connected

to clean supplies. Decoupling capacitors should be

located as close to the device package as possible.

If desired, all supply pins may be connected to the

same supply, but a decoupling capacitor should still

be used on each supply pin.

6.2 Clock Modes

One of the characteristics of a PWM amplifier is

that the frequency content of out-of-band noise

generated by the modulator is dependent on the

PWM switching frequency. The systems designer

will specify the external filter based on this switch-

ing frequency. The obvious implementation in a

digital PWM system is to directly lock the PWM

switching rate to the incoming data sample rate.

However, this would require a tuneable filter to at-

tentuate the switching frequency across the range

of possible sample rates. To simplify the external

filter design and to accommodate sample rates

ranging from 8 kHz to 96 kHz the CS44L10 Con-

troller uses several clock modes that keep the PWM

switching frequency in a small range.

In control port mode, for operation at a particular

sample rate the user selects register settings (refer

to Section 4.9 and Tables 11 and 13) based on their

MCLK and MCLK/LRCK parameters. When us-

ing Stand-Alone mode, refer to Tables 12 and 14

for available clock modes.

6.3 De-Emphasis

The CS44L10 includes on-chip digital de-empha-

sis. Figure 6 shows the de-emphasis curve. The fre-

quency response of the de-emphasis curve will

scale proportionally with changes in sample rate,

Fs.

The de-emphasis feature is included to accommo-

date older audio recordings that utilize pre-empha-

sis equalization as a means of noise reduction.

6.4 PWM PopGuard Transient Control

The CS44L10 uses PopGuard® technology to min-

imize the effects of output transients during pow-

er-up and power-down. This technique minimizes

the audio transients commonly produced by sin-

gle-ended, single-supply converters when it is im-

plemented with external DC-blocking capacitors

connected in series with the audio outputs.

When the device is initially powered-up, the HP_x

outputs are clamped to GND. Following a delay

each output begins to increase the PWM duty cycle

toward the quiescent voltage point. By a speed set

by the RMP_SP bit, the HP_x outputs will later

reach the bias point (50% PWM duty cycle), and

audio output begins. This gradual voltage ramping

allows time for the external DC-blocking capacitor

to charge to the quiescent voltage, minimizing the

power-up transient.

To prevent transients at power-down, the device

must first enter its power-down state. When this oc-

curs, audio output ceases and the PWM duty cycle

26

DS541PP1

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