CS8420-CSR 데이터 시트보기 (PDF) - Cirrus Logic

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CS8420-CSR

Digital Audio Sample Rate Converter

Cirrus Logic 

CS8420

9. CONTROL PORT DESCRIPTION AND TIMING

The control port is used to access the registers, allowing the CS8420 to be configured for the desired operational

modes and formats. In addition, Channel Status and User data may be read and written via the control port. The

operation of the control port may be completely asynchronous with respect to the audio sample rates. However, to

avoid potential interference problems, the control port pins should remain static if no operation is required.

The control port has two modes: SPI and I²C, with the CS8420 acting as a slave device. SPI mode is selected if

there is a high-to-low transition on the AD0/CS pin after the RST pin has been brought high. I²C mode is selected

by connecting the AD0/CS pin to VD+ or DGND, thereby permanently selecting the desired AD0 bit address state.

9.1 SPI Mode

In SPI mode, CS is the CS8420 chip select signal. CCLK is the control port bit clock (input into the CS8420

from the microcontroller), CDIN is the input data line from the microcontroller, CDOUT is the output data line

to the microcontroller. Data is clocked in on the rising edge of CCLK and out on the falling edge.

Figure 22 shows the operation of the control port in SPI mode. To write to a register, bring CS low. The first

7 bits on CDIN form the chip address and must be 0010000b. The eighth bit is a read/write indicator (R/W),

which should be low to write. The next 8 bits form the Memory Address Pointer (MAP), which is set to the

address of the register that is to be updated. The next 8 bits are the data which will be placed into the register

designated by the MAP. During writes, the CDOUT output stays in the Hi-Z state. It may be externally pulled

high or low with a 47 kΩ resistor, if desired.

CS

CCLK

C D IN

C H IP

ADDRESS

0010000

MAP

DATA

R/W

MSB

LSB

b yte 1 b yte n

C H IP

ADDRESS

0010000 R/W

CDOUT

High Impedance

MSB

LSB MSB

LSB

MAP = Memory Address Pointer, 8 bits, MSB first

Figure 22. Control Port Timing in SPI Mode

There is a MAP auto-increment capability, enabled by the INCR bit in the MAP register. If INCR is a zero,

then the MAP will stay constant for successive read or writes. If INCR is set to a 1, then the MAP will auto-

increment after each byte is read or written, allowing block reads or writes of successive registers.

To read a register, the MAP has to be set to the correct address by executing a partial write cycle which

finishes (CS high) immediately after the MAP byte. The MAP auto-increment bit (INCR) may be set or not,

as desired. To begin a read, bring CS low, send out the chip address and set the read/write bit (R/W) high.

The next falling edge of CCLK will clock out the MSB of the addressed register (CDOUT will leave the high-

impedance state). If the MAP auto-increment bit is set to 1, the data for successive registers will appear

consecutively.

30

DS245F4

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