CS8420-CSR 데이터 시트보기 (PDF) - Cirrus Logic
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CS8420-CSR Datasheet PDF : 94 Pages
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8. AES3 TRANSMITTER AND RECEIVER
CS8420
8.1 Sample Rate Converter
The equation for the group delay through the sample rate converter, with the serial ports in Master mode is:
((input interface delay + 43) / Fsi) + ((43 + output interface delay ± 0.5) / Fso)
The unit of delay depends on the frame rate (sample rate) Fs. The AES receiver has a interface delay of 2
frames. The AES transmitter, the serial input port, and the serial output port each have an interface delay
of 1 frame. The ± 0.5 frame delay in the second half of the equation is due to the start-up uncertainty of the
logic within the part.
When using multiple parts together, it is possible to start the parts simultaneously in a fashion that minimizes
the relative group delay between the parts. When multiple parts are started together in the proper way, the
variation in signal delay through the parts is ±1.5 μs.
To start the parts simultaneously, set up each one so that the PLL will lock, with the active input port driving
both output ports. Then simultaneously enable the RUN bits in all of the parts. TCBL on one of the CS8420
parts should be set as an output, while the remaining TCBL pins should be set as inputs. This synchronizes
the AES transmitter on all of the parts.
Depending upon software considerations, it may be advantageous to configure the registers so that an in-
terrupt is generated on the INT pin when lock occurs. The control logic should either poll the unlock bits until
all PLL’s are locked or wait for the interrupts to indicate that all are locked, depending on which approach
you’ve chosen.
When all of the PLL’s are locked, the CS8420’s should be advanced to the next state together. Drive all the
serial control ports together with the same clock and data. Change the configuration in register 03h accord-
ing to Table 1 or Table 2.
Register
(HEX)
01
03
04
11
Initial Value
(HEX)
01 or 00
95
41
10
Value After Advancing to the Running
State, After the PLL’s are Locked (HEX)
01 or 00
81
41
10
Table 1. Minimizing Group Delay Through Multiple CS8420s When Locking to RXP/RXN
Register
(HEX)
01
03
04
11
Initial Value
(HEX)
01 or 00
8A
40
10
Value After Advancing to the Running
State, After the PLL’s are Locked (HEX)
01 or 00
80
40
10
Table 2. Minimizing Group Delay Through Multiple CS8420s When Locking to ILRCK
28
DS245F4
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