CS5540-AS 데이터 시트보기 (PDF) - Cirrus Logic

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CS5540-AS

Low-Power, Low-Voltage, 24 - Bit ∆Σ ADC

Cirrus Logic 

CS5540

2.8 Sleep Mode

The CS5540 features two power consumption

modes: normal and sleep. The normal mode, the

default mode, is entered after a power-on-reset. In

normal mode, the CS5540 performs conversions

and typically consumes 750 µW.

To enter sleep, transmit 8 SCLK’s (low-high tran-

sitions) after SDO falls, indicating that a conver-

sion is complete (32 SCLK’s would be needed to

read the conversion). One conversion cycle later,

when SDO falls again, the part enters sleep, reduc-

ing the consumed power to around 30 µW. During

sleep, most of the analog portion of the chip is pow-

ered down and filter convolutions are halted. While

the part is in the sleep mode, the SDO pin will re-

main in a logic high state, as long as the Chip Select

is enabled.

To exit the sleep mode, transmit 8 more SCLK’s.

Since the sleep mode disables the oscillator, ap-

proximately a 500 ms crystal oscillator start-up de-

lay period is required before the ADC returns to the

normal mode. If an external clock is used, the ADC

will return to normal power mode within 3 milli-

seconds. In either case, the SDO pin will go low to

indicate when new data is available and can be

read.

2.9 Power-Up and Initialization

Care must be exercised to insure that no pins are

ever taken below the negative analog supply (VA-)

potential. The analog and digital supplies should be

applied simultaneously to assure that the power-on

reset circuit will automatically reset the ADC when

both supplies are at acceptable levels.

Conversions will begin once a stable clock is avail-

able to the ADC. If a 32.768 kHz crystal is being

used, it will take approximately 500 ms for the os-

cillator to stabilize and to begin conversions after

power has been applied to the converter. If a

CMOS compatible clock source with no start-up

delay is being used to drive the ADC, then conver-

sions will begin immediately.

Note:

The CS5540 includes an on-chip power on

reset circuit to automatically reset the ADC

shortly after power-up. When power to the

CS5540 is applied, the ADC is held in a reset

condition until the master clock has started

and a counter-timer elapses (i.e. the

counter-timer counts 490 clock cycles to

make sure the oscillator is fully stable).

After a valid reset, the ADC is initialized into the

data state where it begins to continuously calibrate

the ADC and convert the analog input. Once a valid

conversion is complete, monitor the SDO pin for a

falling edge to indicate that the data is ready to be

read.

2.10 PCB Layout

The CS5540 should be placed entirely over an ana-

log ground plane with the DGND pin of the device

connected to the analog ground plane. Place the an-

alog-digital plane split immediately adjacent to the

digital portion of the chip

See the CDB5540/41 data sheet for suggested lay-

out details and refer to Applications Note 18 for

more detailed layout guidelines.

Applications engineering provides a Free and Con-

fidential Schematic Review Service.

16

DS503PP1

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