CS5540-AS 데이터 시트보기 (PDF) - Cirrus Logic

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CS5540-AS

Low-Power, Low-Voltage, 24 - Bit ∆Σ ADC

Cirrus Logic 

CS5540

AIN+

+

AIN-

-

VREF+

Reference +- VREF-

Figure 10. Self Calibration of Gain

2.7.1 Reading Conversions

At the completion of a conversion, SDO will fall to

logic 0 to indicate that the conversion is complete.

Calibration will be transparent to the user. Never-

theless, to read a conversion word, the user must is-

sue 32 SCLK’s. The first 8 SCLKs clear the SDO

flag and read the status flags. Upon the falling edge

of the 8th SCLK, the SDO pin will present the first

bit (MSB) of the conversion word. 24 SCLKs

(high, then low) are then required to read the con-

version word from the port. Upon the falling edge

of the 32nd SCLK, SDO will return high, waiting

till the next conversion is complete before it falls

again.

The user is not required to read every conversion.

If the user chooses not to read a conversion after

SDO falls, SDO will rise one MCLK clock cycle

before the next conversion is completed and then

fall to signal that another conversion word is avail-

able (assuming CS is kept low).

Note:

1) If the user begins to clear the SDO flag and

read the conversion data, this action must be

finished before the conversion cycle which is

occurring in the background is complete if the

user wants to be able to read the new

conversion data.

2) If the multiplexer CHS input of the

converter is switched while it is performing a

conversion, the filter will abort the current

conversion and start a new conversion on the

new channel.

3) If the channel is switched when SDO is

low, SDO will remain low, and the previous

conversion result will remain in the serial port.

SDO will rise one MCLK cycle before the new

channel’s data is ready, then fall to indicate

that the conversion data is available.

2.7.2 Output Coding

The CS5540 outputs a 24-bit two’s-complement

data conversion word. To read a conversion word

the user must read the conversion data register,

which is 24 bits long and outputs the conversions

MSB first. Once a conversion is complete, SDO

falls and 32 SCLK’s are required to read a conver-

sion. The first 8 SCLKs are used to clear an internal

SDO flag and clock out status flags.

The CH (CHannel indicator) bit keeps track of

which input channel was converted (0=AIN1;

1=AIN2).

The OD (Oscillation Detect) bit is set to a logic 1 any

time that an oscillatory condition is detected in the

modulator. This does not occur under normal oper-

ating conditions, but may occur whenever the input

to the converter is extremely overranged. If the OD

bit is set, the conversion data bits can be completely

erroneous. The OD flag bit will be cleared to logic 0

when the modulator becomes stable.

The OF (Overrange Flag) bit is set to a logic 1 any

time the input signal is: 1) more positive than posi-

tive full scale, or 2) more negative than negative

full scale. It is cleared back to logic 0 whenever a

conversion word occurs which is not overranged.

The last 24 SCLKs are used to clock the actual data

out of the conversion data register.

Table 1 and Table 2 illustrate the output coding for

the CS5540. Conversion data is output in two's

complement format.

2.7.3 Digital Filter

The CS5540 filter achieves simultaneous rejection

of 50/60 Hz and provides single conversion settling

at a 6.7 SPS throughput, including auto-calibration.

14

DS503PP1

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