CS4270 데이터 시트보기 (PDF) - Cirrus Logic
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CS4270 Datasheet PDF : 49 Pages
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SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT
(Logic "0" = AGND = 0 V; Logic "1" = VD, CL = 20 pF)
Parameter
Sample Rate
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
MCLK Specifications
MCLK Frequency
(Note 17)
tand-Alone Mode
Control Port Mode
MCLK Duty Cycle
Master Mode
LRCK Duty Cycle
SCLK Period (Note 18)
Symbol
Fs
Fs
Fs
fmclk
fmclk
tsclkw
SCLK Duty Cycle
SCLK falling to LRCK edge
SCLK falling to SDOUT valid
SDIN valid to SCLK rising setup time
SCLK rising to SDIN hold time
Slave Mode
LRCK Duty Cycle
SCLK Period
(Note 17)
Single-Speed Mode
Double-Speed Mode
Quad-Speed Mode
tmslr
tsdo
tsdis
tsdih
tsclkw
tsclkw
tsclkw
SCLK Duty Cycle
SCLK falling to LRCK edge
tslrd
SDOUT valid before SCLK rising
tstp
SDOUT valid after SCLK rising
thld
SDIN valid to SCLK rising setup time
tsdis
SCLK rising to SDIN hold time
tsdih
Min
4
50
100
1.024
1.024
40
-
-
-
-20
-
16
20
40
---------1-----------
( 128 ) F s
(---6---4--1-)---F----s-
(---6---4--1-)---F----s-
45
-20
10
5
16
20
Typ
-
-
-
-
-
50
50
--------1---------
( 64 ) F s
50
-
-
-
-
50
-
-
-
50
-
-
-
-
-
CS4270
Max
Unit
54
kHz
108
kHz
216
kHz
55.296
55.296
60
MHz
MHz
ns
-
%
-
s
-
%
20
ns
32
ns
-
ns
-
ns
60
%
-
s
-
s
-
s
55
ns
20
ns
-
ns
-
ns
-
ns
-
ns
17. In Control Port Mode, MCLK Frequency and Functional Mode Select bits must be configured according
to Table 5, Table 8, and Table 12.
18. tsclkw = tsclkh + tsclkl in Figures 5 and 7.
DS686PP1
17
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