CS4270 데이터 시트보기 (PDF) - Cirrus Logic
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CS4270 Datasheet PDF : 49 Pages
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SWITCHING CHARACTERISTICS - SPITM CONTROL PORT
(Inputs: logic 0 = DGND, logic 1 = VLC)
Parameter
SPI Mode
CCLK Clock Frequency
RST Rising Edge to CS Falling
CCLK Edge to CS Falling
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
Symbol
Min
fsclk
-
tsrs
500
(Note 20)
tspi
500
tcsh
1.0
tcss
20
tscl
82
tsch
82
tdsu
40
(Note 21)
tdh
15
(Note 22)
tr2
-
(Note 22)
tf2
-
Max
6
-
-
-
-
-
-
-
-
100
100
CS4270
Unit
MHz
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
20. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.
21. Data must be held for sufficient time to bridge the transition time of CCLK.
22. For FSCK < 1 MHz
RST
t srs
CS
t spi t css
t scl t sch
t csh
CCLK
t r2
t f2
CDIN
t dsu t dh
Figure 13. SPI Control Port Timing
DS686PP1
21
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