CL-PS7111-VC-A 데이터 시트보기 (PDF) - Cirrus Logic

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CL-PS7111-VC-A

Low-Power System-on-a-Chip

Cirrus Logic 

CL-PS7111

Low-Power System-on-a-Chip

CL2

CL1

t20

t15

t16

t18

t17

t19

t21

FRM

M

DD[3:0]

t22

t23

Figure 6-8. LCD Controller Timing

NOTES:

1) This diagram shows the end of a line.

2) If FRM is high during the CL1 pulse, this marks the first line in the display.

3) CL2 low time is doubled during the CL1 high pulse.

86

ELECTRICAL SPECIFICATIONS

September 1997

PRELIMINARY DATA BOOK v2.0

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