CL-PS7111
Low-Power System-on-a-Chip
MCLK
Word write followed by sequential word write to DRAM (MCLK shown for reference only)
DRA[12:0]
RAS[1:0]
CAS[3:0]
D[31:0]
ROW COL
ROW COL 1
tRC
tRAS
t10
t9
tRP
COL 2
COL n
DATA OUT
t12
t11
tCP
tCAS
tPC
t13
t14
DATA OUT 1
DATA OUT 2
DATA OUT n
NMOE
NMWE
WORD
WRITE
Figure 6-5. DRAM Write Cycles
82
ELECTRICAL SPECIFICATIONS
September 1997
PRELIMINARY DATA BOOK v2.0