CL-PS7111-VC-A 데이터 시트보기 (PDF) - Cirrus Logic
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CL-PS7111-VC-A Datasheet PDF : 105 Pages
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CL-PS7111
Low-Power System-on-a-Chip
Bit Description (cont.)
1:0 Bus Width: The effect of this field is dependent on the two BOOTBIT bits, which can be read in the SYSFLG register.
All bits in the Memory Configuration register are cleared by a system reset, and the state of the BOOTBIT bits is deter-
mined by Port E bits 0 and 1 on the CL-PS7111 during power-on reset. The state of PE1 and PE0 determine whether
the CL-PS7111 is going to boot from either 32-, 16-, or 8-bit-wide ROMs.
See Chapter 6, “ELECTRICAL SPECIFICATIONS” for more details on bus timing.
Bit
BOOTBIT1 BOOTBIT0
10
00
0
0
01
0
0
10
0
0
11
0
0
00
0
1
01
0
1
10
0
1
11
0
1
00
1
0
01
1
0
10
1
0
11
1
0
Expansion Transfer
Mode
32-bit-wide bus access
16-bit-wide bus access
8-bit-wide bus access
Reserved
8-bit-wide bus access
Reserved
32-bit-wide bus access
16-bit-wide bus access
16-bit-wide bus access
32-bit-wide bus access
Reserved
8-bit-wide bus access
Port E Bits 1 and 0 During
NPOR Reset
Low, Low
Low, Low
Low, Low
Low, Low
Low, High
Low, High
Low, High
Low, High
High, Low
High, Low
High, Low
High, Low
56
REGISTER DESCRIPTIONS
September 1997
PRELIMINARY DATA BOOK v2.0
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