CL-PS7111-VC-A 데이터 시트보기 (PDF) - Cirrus Logic
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CL-PS7111-VC-A Datasheet PDF : 105 Pages
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CL-PS7111
Low-Power System-on-a-Chip
5.10 Memory Configuration Register 1 — MEMCFG1
31:24
NCS3 configuration
23:16
NCS2 configuration
15:8
NCS1 configuration
7:0
NCS0 configuration
Expansion and ROM space is selected by one of eight chip selects. One chip select (CS6) is used inter-
nally for the on-chip SRAM, and the configuration is hardwired for 32-bit wide, minimum-wait state oper-
ation. CS7 is used for the on-chip Boot ROM, and the configuration field is hardwired for 8-bit wide,
minimum-wait state operation. Data written to the configuration fields for either CS6 or CS7 are ignored.
Two of the chip selects (NCS4 and NCS5) can be used to access two CL-PS6700 PCMCIA controller
devices, and when either of these interfaces is enabled, the configuration field for the appropriate chip
select in the MEMCFG2 register is ignored. When the PCMCIA1 or 2 control bit in the SYSCON2 register
is disabled, then NCS4 and NCS5 are active as normal and can be programmed using the relevant fields
of MEMCFG2, as for the other four chip selects. All of the six external chip selects are active for
256 Mbytes, and the timing and bus transfer width can be programmed individually. This is accomplished
by programming the width fields contained in two 32-bit registers, MEMCFG1 and MEMCFG2. All bits in
these registers are cleared by a system reset (except for the CS6 and CS7).
The Memory Configuration register 1 is a 32-bit read/write register that sets the configuration of the four
expansion and ROM selects NCS0–3. Each select is configured with a 1-byte field, starting with expan-
sion select 0.
September 1997
PRELIMINARY DATA BOOK v2.0
53
REGISTER DESCRIPTIONS
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