CS42L51-DNZR 데이터 시트보기 (PDF) - Cirrus Logic
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CS42L51-DNZR Datasheet PDF : 88 Pages
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CS42L51
6.19 PCM Channel Mixer (Address 18h)
7
PCMA1
6
PCMA0
5
PCMB1
4
PCMB0
3
ADCA1
2
ADCA0
1
ADCB1
0
ADCB0
Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register.
Channel Mixer (PCMx[1:0] & ADCx[1:0])
Default: 00
PCMA[1:0]
and/or
ADCA[1:0]
00
01
10
11
AOUTA PCMB[1:0] and/or AOUTB
ADCB[1:0]
L
00
L-----+----R---
01
2
10
R
11
R
L-----+----R---
2
L
Function:
Implements mono mixes of the left and right channels as well as a left/right channel swap.
6.20 Limiter Threshold SZC Disable (Address 19h)
7
MAX2
6
MAX1
5
MAX0
4
CUSH2
3
CUSH1
2
CUSH0
1
0
LIM_SRDIS LIM_ZCDIS
Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register.
Maximum Threshold (MAX[2:0])
Default: 000
MAX[2:0]
000
001
010
011
101
101
110
111
Threshold
Setting
(dB)
0
-3
-6
-9
-12
-18
-24
-30
Function:
Sets the maximum level, below full scale, at which to limit and attenuate the output signal at the attack rate.
Bass, Treble and digital gain settings that boost the signal beyond the maximum threshold may trigger an
attack.
DS679F1
67
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