CS44L10 データシートの表示（PDF） - Cirrus Logic
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CS44L10 Datasheet PDF : 34 Pages
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CS44L10
5. PIN DESCRIPTION
Serial Data
Left/Right Clock
Serial Clock
Master Clock
Digital Power
Ground
Interface Power
SCL/DIF0
SDIN 1
LRCK 2
SCLK 3
MCLK 4
VD 5
GND 6
VL 7
SCL/DIF0 8
16 RST
15 GND
14 HP_B
13 VA_HPB
12 VA_HPA
11 HP_A
10 GND
9 SDA/DEM
Reset
Headphone B Ground
Headphone B Output
Headphone B Power
Headphone A Power
Headphone A Output
Headphone A Ground
SDA/DEM
SDIN
LRCK
SCLK
MCLK
VD
GND
VL
HP_A
HP_B
VA_HPA
VA_HPB
RST
Control Port
Definitions
SCL
SDA
Stand Alone
Definitions
DIF0
DEM
DS541PP1
1 Serial Audio Data Input (Input) - Input for two’s complement serial audio data.
2 Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the
serial audio data line. The frequency of the left/right clock must be at the audio sample rate, Fs.
3 Serial Clock (Input) - Serial clock for the serial audio interface.
4 Master Clock (Input) - Clock source for the PWM modulator and digital filters. Table 11, 12, 13
and 14 illustrate several standard audio sample rates and required master clock frequencies.
5 Digital Power (Input) - Positive power supply for the digital section. Refer to "Recommended
Operating Conditions" for appropriate voltages.
6, 10 Ground (Input) - Ground Reference.
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7 Logic Power (Input) - Determines the required signal level for the digital input/output. Refer to
"Recommended Operating Conditions" for appropriate voltages.
11 Headphone Outputs (Output) - PWM Headphone Outputs. An external LC filter should be
14 added to suppress high frequency switching noise. A DC blocking capacitor is also required.
Refer to Typical Connection Diagrams.
12 Headphone Amplifier Power (Input) - Positive power supply for the headphone amplifier.
13 Refer to "Recommended Operating Conditions" for appropriate voltages.
16 Reset (Input) - The device enters a low power mode and all internal registers are reset to their
default settings when low. The control port cannot be accessed when Reset is low. See Sec-
tion 6.5
8 Serial Control Port Clock (Input) - Serial clock for the serial control port. Requires an external
pull-up resistor to VL in Two-Wire mode.
9 Serial Control Data (Input/Output) - SDA is a data I/O line in Two-Wire mode and requires an
external pull-up resistor to the logic interface voltage.
8 Digital Interface Format (Input) - The required relationship between the Left/Right clock, serial
clock and serial data is defined by the Digital Interface Format and the options are detailed
below
DIF0
DESCRIPTION
0 I2S, up to 24-bit data
1 Right Justified, 16-bit Data
FIGURE
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Table 15. Digital Interface Format (Stand-Alone Mode)
9 De-emphasis Control (Input) - Selects the standard 15 µs/50 µs digital de-emphasis filter
response at 44.1 kHz sample rates. NOTE: De-emphasis is not available in Double or Quad
Speed Modes. When DEM is grounded, de-emphasis is disabled.
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