CS8405A-CS データシートの表示（PDF） - Cirrus Logic
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CS8405A-CS Datasheet PDF : 37 Pages
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9. PIN DESCRIPTION - SOFTWARE MODE
SDA / CDOUT
1
AD0 / CS
2
AD2
3
RXP
4
DGND2
5
VD+
6
DGND4
7
DGND3
8
RST
9
NC1
10
NC2
11
ILRCK
12
ISCLK
13
SDIN
14
CS8405A
28
SCL / CCLK
27
AD1 / CDIN
26
TXP
25
TXN
24
H/S
23
VL+
22
DGND
21
OMCK
20
U
19
INT
18
NC5
17
NC4
16
NC3
15
TCBL
VD+
VL+
DGND
DGND2
DGND3
DGND4
RST
H/S
TXN
TXP
OMCK
DS469F2
6 Digital Power (Input) - Digital core power supply. Typically +5.0 V.
23 Logic Power (Input) - Input/Output power supply. Typically +3.3 V or +5.0 V.
22 Ground (Input) - Ground for I/O and core logic.
5
8
7
9 Reset (Input) - When RST is low, the CS8405A enters a low power mode and all internal
states are reset. On initial power up, RST must be held low until the power supply is stable,
and all input clocks are stable in frequency and phase. This is particularly true in hardware
mode with multiple CS8405A devices, where synchronization between devices is important.
24 Hardware/Software Control Mode Select (Input) -Determines the method of controlling the
operation of the CS8405A, and the method of accessing Channel Status and User bit data. In
software mode, device control and CS and U data access is primarily through the control port,
using a microcontroller. Hardware mode provides an alternate mode of operation, and access
to CS and U data is provided by dedicated pins. This pin should be permanently tied to VL+
or DGND.
25 Differential Line Drivers (Output) - These pins transmit biphase encoded data. The drivers
26 are pulled low while the CS8405A is in the reset state.
21 Master Clock (Input) - The frequency must be 256x, 384x, or 512x the sample rate.
25
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