CS8405A-CS データシートの表示（PDF） - Cirrus Logic
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CS8405A-CS Datasheet PDF : 37 Pages
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CS8405A
8.12 Channel Status Data Buffer Control (12h)
7
6
5
4
3
2
1
0
0
0
BSEL
0
0
EFTCI
CAM
0
BSEL - Selects the data buffer register addresses to contain User data or Channel Status data
Default = ‘0’
0 - Data buffer address space contains Channel Status data
1 - Data buffer address space contains User data
Note:
There are separate complete buffers for the Channel Status and User bits. This control bit determines which
buffer appears in the address space.
EFTCI - E to F C-data buffer transfer inhibit bit.
Default = ‘0’
0 - Allow C-data E to F buffer transfers
1 - Inhibit C-data E to F buffer transfers
CAM - C-data buffer control port access mode bit
Default = ‘0’
0 - One byte mode
1 - Two byte mode
8.13 User Data Buffer Control (13h)
7
6
5
4
3
2
1
0
0
0
0
UD
UBM1
UBM0
0
EFTUI
UD - User bit data source specifier
Default = ‘0’
0 - The U pin is an input. The User bit data is latched in on both rising and falling edges of
OLRCK. This setting also chooses the U pin as the source for transmitted U data.
1 - Sets the U data buffer as the source of transmitted U data. The U pin also becomes an
indeterminate output.
UBM1:0 - Sets the operating mode of the AES3 User bit manager
Default = ‘00’
00 - Transmit all zeros mode
01 - Block mode
10 - Reserved
11 - Reserved
EFTUI - E to F U-data buffer transfer inhibit bit (valid in block mode only).
Default = ‘0’
0 - Allow U-data E to F buffer transfers
1 - Inhibit U-data E to F buffer transfer
DS469F2
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