PSD935G3V-C-15UI データシートの表示（PDF） - STMicroelectronics

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PSD935G3V-C-15UI

Configurable Memory System on a Chip for 8-Bit Microcontrollers

STMicroelectronics 

PSD9XX Family

The

PSD935G2

Functional

Blocks

(cont.)

PSD935G2

9.4.5 Ports A, B and C – Functionality and Structure

Ports A and B have similar functionality and structure, as shown in Figure 21. The two

ports can be configured to perform one or more of the following functions:

t MCU I/O Mode

t GPLD Output – Combinatorial PLD outputs.

t PLD Input – Input to the PLDs.

t Address In – Additional high address inputs may be latched by ALE.

t Open Drain/Slew Rate – pins PC[7:0]can be configured to fast slew rate,

pins PA[7:0] and PB[7:0] can be configured to Open Drain

Mode.

Figure 21 Port A, B and C

DATA OUT

REG.

DQ

WR

GPLD OUTPUT

READ MUX

P

D

B

DATA OUT

OUTPUT

MUX

DATA IN

OUTPUT

SELECT

PORT PIN

DIR REG.

DQ

WR

PLD INPUT

52

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