PSD935G3V-C-15UI データシートの表示（PDF） - STMicroelectronics

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PSD935G3V-C-15UI

Configurable Memory System on a Chip for 8-Bit Microcontrollers

STMicroelectronics 

PSD9XX Family

The

PSD935G2

Functional

Blocks

(cont.)

PSD935G2

9.4.3 Port Configuration Registers (PCRs)

Each port has a set of PCRs used for configuration. The contents of the registers can be

accessed by the microcontroller through normal read/write bus cycles at the addresses

given in Table 6. The addresses in Table 6 are the offsets in hex from the base of the

CSIOP register.

The pins of a port are individually configurable and each bit in the register controls its

respective pin. For example, Bit 0 in a register refers to Bit 0 of its port. The three PCRs,

shown in Table 19, are used for setting the port configurations. The default power-up state

for each register in Table 22 is 00h.

Table 19. Port Configuration Registers

Register Name

Control

Direction

Drive Select*

Port

E,F,G

A,B,C,D,E,F,G

A,B,C,D,E,F,G

MCU Access

Write/Read

Write/Read

Write/Read

*NOTE: See Table 22 for Drive Register bit definition.

9.4.3.1 Control Register

Any bit set to ‘0’ in the Control Register sets the corresponding Port pin to MCU I/O Mode,

and a ‘1’ sets it to Address Out Mode. The default mode is MCU I/O. Only Ports E, F and

G have an associated Control Register.

9.4.3.2 Direction Register

The Direction Register controls the direction of data flow in the I/O Ports. Any bit set to ‘1’

in the Direction Register will cause the corresponding pin to be an output, and any bit set

to ‘0’ will cause it to be an input. The default mode for all port pins is input.

Figures 21 and 23 show the Port Architecture diagrams for Ports A/B/C and E/F/G

respectively. The direction of data flow for Ports A, B, C and F are controlled by the

direction register.

An example of a configuration for a port with the three least significant bits set to output

and the remainder set to input is shown in Table 21. Since Port D only contains four pins,

the Direction Register for Port D has only the four least significant bits active.

Table 20. Port Pin Direction Control

Direction Register Bit

Port Pin Mode

0

Input

1

Output

Table 21. Port Direction Assignment Example

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

0

0

0

0

0

Bit 2

1

Bit 1

1

Bit 0

1

50

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