CS8420-CSZ データシートの表示（PDF） - Cirrus Logic

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CS8420-CSZ

Digital Audio Sample Rate Converter

Cirrus Logic 

13.2.1 Pin Description - Hardware Mode 1

CS8420

Overall Device Control:

DFC0, DFC1 - Data Flow Control Inputs

DFC0 and DFC1 inputs determine the major data flow options available in Hardware mode, as shown in Table 5.

S/AES - Serial Audio or AES3 Input Select

S/AES is connected to ground in Hardware mode 1 in order to select the AES3 input.

MUTE - Mute Output Data Input

If MUTE is low, audio data is passed normally. If MUTE is high, both the AES3 transmitted audio data and the serial

audio output port data is set to digital zero.

OMCK - Output Section Master Clock Input

Output section master clock input. The frequency must be 256x the output sample rate (Fso).

AES3/SPDIF Receiver Interface:

RXP, RXN - Differential Line Receiver Inputs

Differential line receiver inputs, carrying AES3 type data.

RMCK - Input Section Recovered Master Clock Output

Input section recovered master clock output. Will be at a frequency of 256x the input sample rate (Fsi). This is also

a start-up option pin and requires a pull-up or pull-down resistor.

DS245F4

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