CS8416-CS データシートの表示（PDF） - Cirrus Logic

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CS8416-CS

192 kHz Digital Audio Interface Receiver

Cirrus Logic 

CS8416

AUDIO

96KHZ

RCBL

U

C

TX

SDOUT

OLRCK

OSCLK

OMCK

RMCK

15 Audio Channel Status Bit(output) – When low, a valid linear PCM audio stream is indicated.

16 96 khz Sample Rate Detect(output) - if input sample rate is ≤ 48 KHz, ouputs a “0”. Outputs a “1” if

the sample rate is ≥ 88.1 KHz. Otherwise output indeterminate.

17 Receiver Channel Status Block (Output) -Indicates the beginning of a received channel status

block. RCBL goes high two frames after the reception of a Z preamble, remains high for 16 frames

and then returns low for the remainder of the block. RCBL changes on rising edges of RMCK.

18 User Data (Output) - Outputs user data from the AES3 receiver, clocked by the rising and falling

edges of OLRCK.

19 Channel Status Data (Output) - Outputs channel status data from the AES3 receiver, clocked by the

ris ing and falling edges of OLRCK.

20 S/PDIF MUX Pass through (Output)

26 Serial Audio Output Data (Output) - Audio data serial output pin. This pin must be pulled to low to

DGND through a 47 KΩ resistor.

28 Serial Audio Output Left/Right Clock (Input/Output) - Word rate clock for the audio data on the

SDOUT pin. Frequency will be the output sample rate (Fs).

27 Serial Audio Output Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT pin.

25 System Clock (Input) - When the OMCK System Clock Mode is enabled using the SWCLK bit in the

Control 1 register, the clock signal input on this pin is output through RMCK. OMCK serves as

reference signal for OMCK/RMCK ratio expressed in register 24

24 Recovered Master Clock (Output) - Recovered master clock output when PLL is locked to the

incoming AES3 stream. Frequency is 128/256x the sample rate (Fs).

DS578PP2

39

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