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CS5560-ISZ データシートの表示(PDF) - Cirrus Logic

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CS5560-ISZ Datasheet PDF : 32 Pages
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7/31/07
CS5560
3.7 Typical Connection Diagrams
The following figure depicts the CS5560 powered from bipolar analog supplies, +2.5 V and - 2.5 V.
R1
C1
R1
C1
49.9
60pF
4.99k
4.99k
49.9
+2.048 V
0V
-2.048 V
+2.048 V
0V
-2.048 V
60pF
4.99k
4.99k
+2.5 V
+4.096
Voltage
Reference
(NOTE 1)
-2.5 V
4700pF
C0G
AIN+
4700pF
C0G
AIN-
(V+) Buffers On
BUFEN
(V-) Buffers Off
VREF+
10 µF
0.1 µF
VREF-
CS5560
SMODE
CS
4SCLK
4SDO
RDY
CONV
CAL
BP/UP
SLEEP
RST
MCLK
TST
+2.5 V
+3.3 V to +1.8 V
10
0.1 µF
0.1 µF
10
0.1 µF
X7R
V1+
V2+
V2-
DCR
VL
0.1 µF
V1-
VLR
-2.5 V
NOTES
1. See Section 3.4 Voltage Reference for information on required
voltage reference performance criteria.
2.Locate capacitors so as to minimize loop length.
3. The ±2.5 V supplies should also be bypassed to ground at the converter.
4. VLR and the power supply ground for the ±2.5 V should be
connected to the same ground plane under the chip.
5. SCLK and SDO may require pull-down resistors in some applications.
6. An RC input filter can be used to band limit the input to reduce noise.
Select R to be equal to the parallel combination of the feedback of the
feedback resistors 4.99k || 4.99k = 2.5k⎠ ⎠
Figure 7. CS5560 Configured Using ±2.5V Analog Supplies
20
DS713A5

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