CS4385(2004) データシートの表示（PDF） - Cirrus Logic
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CS4385 Datasheet PDF : 56 Pages
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CS4385
5.4 DSD Control (address 04h)
7
DSD_DIF2
0
6
DSD_DIF1
0
5
DSD_DIF0
0
4
DIR_DSD
0
3
2
1
0
STATIC_DSD INVALID_DSD DSD_PM_MD DSD_PM_EN
1
1
0
0
5.4.1 DSD MODE DIGITAL INTERFACE FORMAT (DSD_DIF)
Default = 000 - Format 0 (64x oversampled DSD data with a 4x MCLK to DSD data rate)
Function:
The relationship between the oversampling ratio of the DSD audio data and the required Master clock to
DSD data rate is defined by the Digital Interface Format pins.
The DSD/PCM bit determines whether PCM or DSD mode is selected.
DIF2
0
0
0
0
1
1
1
1
DIF1
0
0
1
1
0
0
1
1
DIFO
0
1
0
1
0
1
0
1
DESCRIPTION
64x oversampled DSD data with a 4x MCLK to DSD data rate
64x oversampled DSD data with a 6x MCLK to DSD data rate
64x oversampled DSD data with a 8x MCLK to DSD data rate
64x oversampled DSD data with a 12x MCLK to DSD data rate
128x oversampled DSD data with a 2x MCLK to DSD data rate
128x oversampled DSD data with a 3x MCLK to DSD data rate
128x oversampled DSD data with a 4x MCLK to DSD data rate
128x oversampled DSD data with a 6x MCLK to DSD data rate
Table 8. Digital Interface Formats - DSD Mode
5.4.2 DIRECT DSD CONVERSION (DIR_DSD)
Function:
When set to 0 (default), DSD input data is sent to the DSD processor for filtering and volume control func-
tions.
When set to 1, DSD input data is sent directly to the switched capacitor DACs for a pure DSD conversion.
In this mode the full scale DSD and PCM levels will not be matched (see Section 2), the dynamic range
performance may be reduced, the volume control is inactive, and the 50 kHz low pass filter is not available
(see section 2 for filter specifications).
5.4.3 STATIC DSD DETECT (STATIC_DSD)
Function:
When set to 1 (default), the DSD processor checks for 28 consecutive zeroes or ones and, if detected,
sends a mute signal to the DACs. The MUTEC pins will eventually go active according to the DAMUTE
register.
When set to 0, this function is disabled.
40
DS671A1
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