CS4385(2004) データシートの表示（PDF） - Cirrus Logic

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CS4385
(Rev.:2004)

114 dB, 192 kHz 8-Channel D/A Converter

Cirrus Logic 

CS4385

3.13.2.2 I2C Read

To read from the device, follow the procedure below while adhering to the control port

Switching Specifications.

1) Initiate a START condition to the I2C bus followed by the address byte. The upper

6 bits must be 001100. The seventh bit must match the setting of the AD0 pin, and the

eighth must be 1. The eighth bit of the address byte is the R/W bit.

2) After transmitting an acknowledge (ACK), the device will then transmit the contents

of the register pointed to by the MAP. The MAP register will contain the address of the

last register written to the MAP, or the default address (see section 3.13.1) if an I2C

read is the first operation performed on the device.

3) Once the device has transmitted the contents of the register pointed to by the MAP,

issue an ACK.

4) If the INCR bit is set to 1, the device will continue to transmit the contents of succes-

sive registers. Continue providing a clock and issue an ACK after each byte until all the

desired registers are read, then initiate a STOP condition to the bus.

5) If the INCR bit is set to 0 and further I2C reads from other registers are desired, it is

necessary to initiate a repeated START condition and follow the procedure detailed

from steps 1 and 2 from the I2C Write instructions followed by step 1 of the I2C Read

section. If no further reads from other registers are desired, initiate a STOP condition

to the bus.

Note 1

SDA

ADDR

001100 AD0

R/W ACK

DATA

1-8

ACK

DATA

1-8

ACK

SCL

S ta rt

Stop

N ote: If operation is a w rite, th is byte contains the M em ory A ddress P ointer, M A P.

Figure 26. Control Port Timing, I2C Mode

32

DS671A1

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