CS62180B-IP データシートの表示（PDF） - Cirrus Logic
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CS62180B-IP Datasheet PDF : 52 Pages
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CS62180A
CS62180B
7 (MSB)
BVCS
1=
BVCR
Saturation
6
ECS
ECR
Saturation
5
4
3
RYEL RCL FERR
Yellow Alarm Carrier Loss Frame Error
Detected
Detected
Detected
2
1
B8ZSD RBL
B8ZS/COFA Blue Alarm
Detected Detected
0 (LSB)
RLOS
Resync in
progress
Figure 21. Receive Status Register (RSR)
is correct. Since the frame alignment is correct
no OOF event or auto resync occurs. A forced
resync will force the 62180B to synchronize to
the frame and multiframe alignment.
T1DM Resync
Resync is based upon the 6-bit sync word in
channel 24. Once the sync word is recognized,
6 consecutive frames with the correct sync word
and FS/FT bits are required before declaring syn-
chronization. RCR.2 must be set to "0". RCR.3
is ignored. When frame synchronization is de-
clared, RLOS goes low and RFSYNC is output
concurrent with the f-bits. However, the super-
frame output clocks (RMSYNC, RSIGFR and
RSIGSEL) are held low for an additional short
period of time until superframe synchronization
is found.
Receive Status Register (RSR)
The CS62180A and CS62180B monitors the in-
coming T1 data for a number of error conditions.
These alarms are recorded in the Receive Status
Register (RSR), and output in real time on the
status pins: RYEL, RCL, RBV, RFER, and
RLOS. Three presettable counters are provided
which count the number of occurrences of Bipo-
lar Violations, Framing and CRC errors. The
Receive Interrupt Mask Register, RIMR, can be
set to specify which of the eight errors recorded
in the RSR will generate a hardware interrupt on
INT. When operating in hardware mode, all
these registers are cleared, and only the status
pins provide real time alarm information.
RSER
Errored F-bit
F
2nd Frame
Loss of Carrier
(32nd or 128th "0")
F
"0" "0" "0" "1"
Bipolar Violation
F
RCLK
RMSYNC
RFSYNC
RFER
RBV
RCL
RLOS
Resync
OOF
Resync
Reframed
Loss of Carrier (RCL) Bipolar Violation
Figure 22. Receive Status Pin Timing
CRC Error
28
DS225PP1
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