CS62180B-IP データシートの表示（PDF） - Cirrus Logic

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CS62180B-IP

T1 Framer

Cirrus Logic 

CS62180A

CS62180B

7 (MSB) 6

5

ARC OOF

0 OOF/RCL 0 2 out of 4 0

1 OOF only 1 2 out of 5 1

RCI

Disabled

Enabled

4

RCS

0 Idle (7F)

1 Milliwatt

3

2

SYNCC SYNCT

0 Ft/FPS only 0 10 bits

1 Fs/CRC 1 24 bits

1

0 (LSB)

SYNCE RESYNC

0 Autoresync rising edge

1 Disabled triggered.

Figure 19. Receive Control Register (RCR)

circuit shown in Figure A1 in the Applications

section.

T1DM Timing

The 8 kHz link data can be sampled on RLINK

using the falling edge of RFSYNC. Refer to Fig-

ure 18 and "Switching Characteristics–Receiver"

for timing diagrams. RSIGFR, RSIGSEL and

RLCLK serve no purpose in the T1DM mode

and may be ignored.

Receive Control Register (RCR)

The RCR provides for insertion of either idle or

digital milliwatt codes, and has six different con-

trol bits which enable a large number of options

for tailoring the receiver resync behavior. Refer

to Figure 19 for an overview of the RCR.

sponds to a received DS0 channel: RMR1.0 =

channel 1, RMR1.7 = channel 8, RMR2.7 =

channel 16, etc. A channel is marked for code

insertion by setting the bit which corresponds to

that channel in the appropriate RMR register.

When RCR.5 is clear, code insertion is disabled,

and the contents of the RMR registers are ig-

nored.

RCS (RCR.4) selects whether to insert an idle

code, or a digital milliwatt code, into the individ-

ual DS0 channels marked in the three Receive

Mark Registers (RMR1 - RMR3). Clearing

RCR.4 will select for an idle code (7F hex) to be

inserted into marked channels. Setting RCR.4 to

a "1" will cause a digital milliwatt code (µ-LAW

format) to be inserted into all marked channels.

Receiver Synchronization

Receive Code Select/Insert

RCR.4: RCS

RCR.5: RCI

When enabled via RCI (RCR.5), the Receive

Mark Registers are used to select individual DS0

channels for insertion of idle or digital milliwatt

codes, as selected via RCS (RCR.4). There are

three RMR registers: RMR1, RMR2, and RMR3

(Figure 20). Each bit in the RMR registers corre-

The receiver monitors the incoming signal for

loss of frame alignment (based on FT or FPS bits

only). Unless auto resync has been disabled via

RCR.1 (see below), the receiver will automat-

ically initiate a search for the correct framing

alignment when loss of synchronization is de-

tected, and RLOS (pin 39) will go high until a

new framing alignment is declared.

7 (MSB) 6

5

4

3

2

1

0 (LSB)

RMR1 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1

RMR2 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9

RMR3 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17

"0" = Normal "1" = Corresponding DS0 Channel is Replaced with Idle or Digital Milliwatt Code. (See RCR.4 and RCR.5)

Figure 20. Receive Mark Registers (RMR1 - RMR3)

DS225PP1

25

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