STM8L001J3 Datasheet - STMicroelectronics

Description
   The STM8L001J3 low-power microcontroller features the enhanced STM8 CPU core providing increased processing power (up to 16 MIPS at 16 MHz) while maintaining the advantages of a CISC architecture with improved code density, a 24-bit linear addressing space and an optimized architecture for low power operations.

   The family includes an integrated debug module with a hardware interface (SWIM) which allows non-intrusive in-application debugging and ultra fast Flash programming.

   All STM8L001J3 microcontrollers feature low power low-voltage single-supply program Flash memory. The 8-Kbyte devices embed data EEPROM.

   The STM8L001J3 low power microcontroller is based on a generic set of state-of-the-art peripherals. The modular design of the peripheral set allows the same peripherals to be found in different ST microcontroller families including 32-bit families. This makes any transition to a different family very easy, and simplified even more by the use of a common set of development tools.

   All STM8L low power products are based on the same architecture with the same memory mapping and a coherent pinout.