STLVDS385 Datasheet - STMicroelectronics

DESCRIPTION
The STLVDS385 transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. At a transmit clock frequency of 85 MHz, 24 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 595 Mbps per LVDS data channel. Using a 85 MHz clock, the data throughput is 297.5 Mbytes/sec. The transmitter can be programmed for Rising edge strobe or Falling edge strobe through a dedicated pin. A Rising edge or Falling edge strobe transmitter will inter operate with a Falling edge strobe Receiver without any translation logic.

■ 20 TO 85 MHz SHIFT CLOCK SUPPORT
■ BEST–IN–CLASS SET & HOLD TIMES ON TxINPUTs
■ Tx POWER CONSUMPTION <130 mW (typ) @85MHz GRAYSCALE
■ Tx POWER-DOWN MODE <200µW (max)
■ SUPPORTS VGA, SVGA, XGA aND SINGLE/DUAL PIXEL SXGA.
■ NARROW BUS REDUCES CABLE SIZE AND COST
■ UP TO 2.38 Gbps THROUGHPUT
■ UP TO 297.5 Megabytes/sec BANDWIDTH
■ 345 mV (typ) SWING LVDS DEVICES FOR LOW EMI
■ PLL REQUIRES NO EXTERNAL COMPONENTS
■ COMPATIBLE WITH TIA/EIA -644 LVDS STANDARD