ST20-C1 Datasheet - STMicroelectronics

Introduction
This manual provides a summary and reference to the ST20 architecture and instruction set for the ST20-C1 core.
ST20 is a technology for building successful embedded VLSI designs. ST20 devices comprise a collection of VLSI macro-cells connected through a high-performance onchip bus. This architecture allows the easy construction of both general purpose (e.g. ST20-MC1 micro-controller) and application specific devices (e.g. ST20-TPx digital set top box family).

ST20-C1 features
The ST20-C1 has the following features:
• It is implemented as a 2-way superscalar, 3-stage pipeline, with an internal 16- word register cache. This architecture can sustain 4 instructions in progress, with a maximum of 2 instructions completing per cycle.
• It uses a variable length instruction coding scheme based on 8-bit units which gives excellent static and dynamic code size. Instructions take between 1 and 8 units to code, with an average of 1.25 units (10 bits) per instruction.
• It provides flexible prioritized vectored interrupt capabilities. The worst case interrupt latency is 0.5 microseconds (at 33 Mhz operating frequency).
• It provides extensive instruction level support for 16-bit digital signal processing (DSP) algorithms.
• It is particularly suitable for low power and battery-powered applications, with low core operating power, and sophisticated power management facilities.
• It provides extensive real-time debugging capability through the optional ST20 diagnostic controller unit (DCU) macro-cell, which supports fully non-intrusive breakpoints, watchpoints and code tracing.
• It has a flexible and powerful built-in hardware scheduler. This is a light-weight real-time operating system (RTOS) directly implemented in the microcode of the ST20-C1 processor. The hardware scheduler can be customized and provides support for software schedulers.
• It provides a built-in user-programmable 32-bit input/output register providing system control and communication capability directly from the CPU.